Specification
Bluetooth® radio
- Common TX/RX terminal simplifies external matching; eliminates external antenna switch
- BIST minimises production test time
- Bluetooth v2.0+EDR specification compliant
Transmitter
- +6.5dBm RF transmit power with level control from on-chip 6-bit DAC over a dynamic range >30dB
- Class 2 and Class 3 support without the need for an external power amplifier or TX/RX switch
Receiver
- Integrated channel filters
- Digital demodulator for improved sensitivity and co-channel rejection
- Real time digitised RSSI available on HCI interface
- Fast AGC for enhanced dynamic range
- -90dBm receive sensitivity
Synthesiser
- Fully integrated synthesiser requires no external VCO, varactor diode, resonator or loop filter
- Compatible with crystals between 8 and 32MHz (in multiples of 250kHz) or an external clock
- Accepts 7.68, 14.44, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8 and 38.4MHz TCXO frequencies for GSM and CDMA devices with sinusoidal or logic level signals
Baseband and software
- External Flash extendable to 32Mbit
- Internal 48kbyte RAM, allows full speed data transfer, mixed voice/data and full piconet support
- Logic for forward error correction, header error control, access code correlation, CRC, demodulation, encryption bit stream generation, whitening and transmit pulse shaping
- Transcoders for A-law, µ-law and linear voice from host and A-law, µ-law and CVSD voice over air
Physical interfaces
- Synchronous serial interface up to 4M data rate
- Optional I2C compatible interface
- UART interfaces with programmable data rate up to 3M with an optional bypass mode
- Full speed USB v1.1 interface
- Bi-directional serial programmable audio interface supporting PCM, I2S and SPDIF formats
- Two LED drivers with faders
Kalimba DSP
- Very low power Kalimba DSP co-processor, 64MIPS, 24-bit fixed point core
- SBC decode takes approximately 4mW power consumption while streaming music
- Single cycle MAC; 24 x 24-bit multiply and 56-bit accumulator
- 32-bit instruction word, dual 24-bit data memory
- 24kbyte (6kword) program RAM, 36Kbyte + 48kbyte (16kword + 12kword) data RAM
- 64words x 32-bit program memory cache when executing from Flash or SDRAM
Stereo audio CODEC
- 16-bit internal stereo CODEC
- Dual ADC and DAC for stereo audio
- Integrated amplifiers for driving 16Ω speakers; no need for external components
- Support for single-ended speaker termination and line output
- Integrated low-noise microphone bias
- Standard sample rates of 8kHz, 11.025kHz, 16kHz, 22.05kHz, 32kHz, 44.1kHz and 48kHz (DAC only)
- -95dB SNR, 0.007% SNR for DAC
Auxiliary features
- User space on processor for customer applications
- Crystal oscillator with built-in digital trimming
- Power management includes digital shutdown and wake up commands with an integrated low power oscillator for ultra-low power Park/Sniff/Hold mode
- Clock request output to control external clock
- On-chip regulators: 1.5V output from 1.8V to 2.7V
- input and 1.8V output from 2.7V to 4.5V input
- On-chip high-efficiency switched-mode regulator; 1.8V output from 2.7V to 4.4V input
- Power-on-reset cell detects low supply voltage
- 10-bit ADC and 8-bit DAC available to applications
- On-chip charger for lithium ion/polymer batteries
Bluetooth stack
CSR's Bluetooth Protocol Stack runs on the on-chip MCU in a variety of configurations:
- Standard HCI (UART or USB)
- Audio CODEC echo-noise cancellation algorithms running on the DSP
Package options
- TFBGA, 8 x 8 x 1.2mm, 0.5mm pitch

